DS200SDCCG1AFD燃機模塊,GE使用方法
VMEchip2中提供了看門狗定時器功能。當看門狗計時器已啟用，必須在編程時間內(nèi)通過軟件重置，或它超時了?？撮T狗可以編程生成系統(tǒng)復(fù)位*信號、本地重置信號或板故障（如果超時）。參考VMEchip2MVME197LE、MVME197DP和MVME197SP單板中的章節(jié)計算機程序員詳細編程參考指南信息軟件可編程硬件中斷8個軟件可編程硬件中斷由VMEchip2。這些中斷允許軟件創(chuàng)建硬件中斷。請參閱MVME197LE、MVME197DP和MVME197SP單板計算機程序員參考指南編程信息。
DS200SDCCG1AFD燃機模塊處理器總線超時總線開關(guān)為處理器總線提供總線超時電路。什么時候通過總線開關(guān)中的BTIMER寄存器啟用，計時器開始計數(shù)
當DBB*被斷言時，如果循環(huán)未終止（TA*、TEA*、或TRTRY*斷言）在編程的超時時間之前，TEA*被斷言。如果訪問到本地外圍總線，則禁用該計時器。
本地外圍總線超時MVME197LE為處理器總線（MC88110）提供超時功能總線）和本地外圍總線（MC68040兼容總線）。當計時器啟用，總線訪問超時，傳輸錯誤確認（TEA）信號生成。對于本地外圍總線，軟件可以選擇8微秒、64微秒、256微秒或無限長的超時值。當?shù)赝鈬偩€計時器在VMEbus綁定周期內(nèi)不工作。VME總線綁定周期由VMEbus訪問計時器和VMEbus全局計時器計時計時器。中斷源MVME197LE微處理器中斷通過總線開關(guān)傳輸。他們可能來自內(nèi)部總線開關(guān)源以及PCCCip2（IPL總線開關(guān)的輸入）、VMEchip2（總線開關(guān)的XIPL輸入）和
其他外部來源（PALINT和IRQ）。總線開關(guān)也可能產(chǎn)生從中止按鈕開關(guān)發(fā)送到微處理器的不可屏蔽中斷（NMI）信號。請參閱中的總線開關(guān)、PCCCIP2和VMEchip2章節(jié)MVME197LE、MVME197DP和MVME197SP單板計算機程序員參考指南，了解更多詳細信息。連接器
MVME197LE有兩個64位DIN接頭：P1和P2。連接器P1行A、B、C和連接器P2行B提供VMEbus互連。連接器P2第A行和第C行提供到SCSI總線的互連，即串行總線端口、以太網(wǎng)接口和Centronics打印機。有一個249針帶有MC88110總線接口的夾層連接器（J2）。這個閣樓
連接器用于其他MVME197模塊擴展。在MVME197LE上還有一個20針通用接頭（J1），提供互連至LED以及復(fù)位和中止信號。此連接器是MVME197系列中的其他模塊不同。參考電路板特定SIMVME197單板計算機支持信息手冊詳細的連接器信號描述。
Watchdog Timer
A watchdog timer function is provided in the VMEchip2. When the watchdog
timer is enabled, it must be reset by software within the programmed time or
it times out. The watchdog can be programmed to generate a SYSRESET*
signal, local reset signal, or board fail if it times out. Refer to the VMEchip2
chapter in the MVME197LE, MVME197DP, and MVME197SP Single Board
Computers Programmer’s Reference Guide for detailed programming
information.
Software-Programmable Hardware Interrupts
Eight software-programmable hardware interrupts are provided by the
VMEchip2. These interrupts allow software to create a hardware interrupt.
Refer to the VMEchip2 chapter in the MVME197LE, MVME197DP, and
MVME197SP Single Board Computers Programmer’s Reference Guide for detailed
programming information.
Processor Bus Timeout
The BusSwitch provides a bus timeout circuit for the processor bus. When
enabled by the BTIMER register in the BusSwitch, the timer starts counting
when DBB* is asserted, and if the cycle is not terminated (TA*, TEA*, or
TRTRY* asserted) before the programmed timeout period, TEA* is asserted.
This timer is disabled if the access goes to the local peripheral bus.
Local Peripheral Bus Timeout
The MVME197LE provides a timeout function for the processor bus (MC88110
bus) and for the local peripheral bus (MC68040 compatible bus). When the
timer is enabled and a bus access times out, a Transfer Error Acknowledge
(TEA) signal is generated. The timeout value is selectable by software for 8μsec, 64 μsec, 256 μsec, or infinite for the local peripheral bus. The local
peripheral bus timer does not operate during VMEbus bound cycles. VMEbus
bound cycles are timed by the VMEbus access timer and the VMEbus global
timer.
Interrupt Sources
MVME197LE MPU interrupts are channeled through the BusSwitch. They
may come from internal BusSwitch sources as well as from the PCCchip2 (IPL
inputs to the BusSwitch), the VMEchip2 (XIPL inputs to the BusSwitch), and
other external sources (PALINT and IRQ). The BusSwitch may also generate
