DS200TBQCG1AAA燃機(jī)卡件,GE怎么使用
內(nèi)存映射有三種觀點(diǎn)：1）所有通過(guò)處理器總線（MC88110總線）查看的資源，2）映射從本地外圍總線查看車載/非車載資源（MC68040兼容總線），以及3）車載資源映射為由VMEbus主機(jī)查看（VMEbus內(nèi)存映射）。處理器總線內(nèi)存映射應(yīng)小心，因?yàn)樗腥齻€(gè)地圖都是可編程的。它是建議從處理器總線直接映射到本地應(yīng)使用外圍總線。MVME197LE設(shè)備的內(nèi)存映射如下所示桌子。表1-2是從$00000000到$ffffff的整個(gè)地圖。
DS200TBQCG1AAA燃機(jī)卡件許多領(lǐng)域的地圖是用戶可編程的，建議使用如表所示。這是假設(shè)處理器和本地外圍總線和本地外圍總線與VMEbus之間。這個(gè)緩存抑制功能可在MC88110中編程。車載輸入/輸出空間必須標(biāo)記為緩存禁止，并在其頁(yè)表中序列化。表1-3進(jìn)一步定義本地設(shè)備的映射。1、該區(qū)域可由用戶編程。建議的用途是如表所示。DRAM解碼器已編程通過(guò)ECDM I2CBus接口在DCAM中。這個(gè)處理器總線到本地外圍總線和本地
外圍總線到處理器總線解碼器是在總線開(kāi)關(guān)中編程。本地外圍設(shè)備VMEbus（主）和VMEbus到本地外圍總線（從）解碼器在VMEchip2中編程。2、尺寸為近似值。3.緩存抑制取決于映射區(qū)域中的設(shè)備。4、該區(qū)域未解碼。如果訪問(wèn)這些位置并且本地外圍總線計(jì)時(shí)器啟用，循環(huán)超時(shí)并由TEA信號(hào)終止。該區(qū)域可通過(guò)總線開(kāi)關(guān)進(jìn)行用戶編程。默認(rèn)大小為4MB。有關(guān)寄存器位的完整描述，請(qǐng)參閱特定芯片的適當(dāng)數(shù)據(jù)表。對(duì)于更詳細(xì)的內(nèi)存映射請(qǐng)參閱詳細(xì)的MVME197LE中的外圍設(shè)備內(nèi)存映射，MVME197DP和MVME197SP單板計(jì)算機(jī)程序員參考指南。2.Address是指向設(shè)備的物理地址。它是從MC88110轉(zhuǎn)換總線開(kāi)關(guān)后設(shè)備的地址。寫入VMEchip2中的LCSR必須為32位。8位或16位的LCSR寫入以TEA信號(hào)終止。對(duì)GCSR的寫入可以是8位、16位或32位。讀取到LCSR和GCSR可以是8、16或32位。4、該區(qū)域不返回確認(rèn)信號(hào)。如果處理器總線超時(shí)計(jì)時(shí)器已啟用，訪問(wèn)時(shí)間輸出并由TEA信號(hào)終止。5、尺寸為近似值。6.82596CA的端口命令必須寫成兩個(gè)16位寫入：第一個(gè)上字，第二個(gè)下字。7.DROM（啟動(dòng)ROM）在本地外圍總線重置。DROM顯示為0，直到DR0位在PCCchip2中被清除。DR0位為位于地址0位D15。DROM必須是在0時(shí)禁用，然后訪問(wèn)DRAM。
There are three points of view for the memory maps: 1) the mapping of all
resources as viewed by the Processor Bus (MC88110 bus), 2) the mapping of
onboard/off-board resources as viewed from the Local Peripheral Bus
(MC68040 compatible bus), and 3) the mapping of onboard resources as
viewed by VMEbus Masters (VMEbus memory map).
Processor Bus Memory Map
Care should be taken, since all three maps are programmable. It is
recommended that direct mapping from the Processor Bus to the Local
Peripheral Bus be used.The memory maps of MVME197LE devices are provided in the following
tables. Table 1-2 is the entire map from $00000000 to $FFFFFFFF. Many areas
of the map are user-programmable, and suggested uses are shown in the table.
This is assuming no address translation is used between the processor and
local peripheral bus and between the local peripheral bus and VMEbus. The
cache inhibit function is programmable in the MC88110. The onboard I/O
space must be marked cache inhibit and serialized in its page table. Table 1-3
further defines the map for the local devices.1. This area is user-programmable. The suggested use is
shown in the table. The DRAM decoder is programmed
in the DCAM through the ECDM I2CBus interface. The
Processor Bus to Local Peripheral Bus and the Local
Peripheral Bus to Processor Bus decoders are
programmed in the BusSwitch. The Local Peripheral to
VMEbus (master) and VMEbus to Local Peripheral Bus
(slave) decoders are programmed in the VMEchip2.
2. Size is approximate.
3. Cache inhibit depends on devices in area mapped.
4. This area is not decoded. If these locations are accessed
and the local peripheral bus timer is enabled, the cycle
times out and is terminated by a TEA signal.
5. This area is user programmable via the BusSwitch.
Default size is 4 megabytes.For a complete description of the register bits, refer to
the appropriate data sheet for the specific chip. For a
more detailed memory map refer to the detailed
peripheral device memory maps in the MVME197LE,
MVME197DP, and MVME197SP Single Board
Computers Programmer’s Reference Guide.
2. Address is the physical address going to the device. It is
after the BusSwitch translation from the MC88110
address to the device seen address.Writes to the LCSR in the VMEchip2 must be 32 bits.
LCSR writes of 8 or 16 bits terminate with a TEA signal.
Writes to the GCSR may be 8, 16, or 32 bits. Reads to the
LCSR and GCSR may be 8, 16, or 32 bits.
4. This area does not return an acknowledge signal. If the
processor bus timeout timer is enabled, the access times
out and is terminated by a TEA signal.
5. Size is approximate.
6. Port commands to the 82596CA must be written as two
16-bit writes: upper word first and lower word second.
7. DROM (BOOT ROM) appears at $0 following a local
peripheral bus reset. The DROM appears at 0 until the
DR0 bit is cleared in the PCCchip2. The DR0 bit is
located at address 0 bit D15. The DROM must be
disabled at 0 before the DRAM is accessed.
