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HONEYWELL 51198685-100控制模塊
XVME-660 VME總線Intel?Celeron?/與奔騰®；III PC兼容的VME總線處理器模塊結(jié)合了VME總線的高性能和加固封裝擁有IBM PC/AT標準的廣泛應(yīng)用軟件基礎(chǔ)。它集成了最新的處理器和芯片組技術(shù)。模塊功能
XVME-660具有以下特點：
基于Intel Celeron 566 MHz或Pentium III 700 MHz Socket 370的CPU66 MHz（賽揚處理器）或100 MHz（奔騰III處理器）前端總線高達256 MB SDRAM（一個144針SODIMM）128 KB（賽揚處理器）或256 KB（奔騰III處理器）片上二級緩存具有4 MB SDRAM的高性能64位AGP圖形控制器PCI增強型IDE控制器與DMA-33 PCI SCSI控制器，16位UltraSCSI，最高40 MBps帶前置RJ-45連接器的10/100 Mbps PCI以太網(wǎng)控制器IDE壓縮閃存站點（使用輔助IDE控制器）
PCI到VME總線接口與DMA兩個高速16550兼容串行端口；COM1可配置為RS-485或RS-232C通用串行總線（USB）端口EPP/ECP可配置并行端口PS/2風(fēng)格鍵盤和鼠標端口
Industry Pack（IP）擴展站點PCI夾層卡（PMC）擴展站點（5 V）看門狗定時器可配置硬件字節(jié)交換邏輯建筑學(xué)CPU芯片Intel Pentium III處理器集成了P6 Dynamic Execution微體系結(jié)構(gòu)、雙處理器獨立總線（DIB）體系結(jié)構(gòu)，多事務(wù)系統(tǒng)總線，Intel MMX? 媒體增強技術(shù)和“英特爾處理器序列號”。此外，它還提供互聯(lián)網(wǎng)數(shù)據(jù)流單指令多數(shù)據(jù)擴展指令集，70條新指令支持高級成像，3D、流式音頻和視頻以及語音識別。Intel Pentium III處理器還有兩個16 KB的一級緩存、指令和數(shù)據(jù)，以及一個256 KB的高級傳輸緩存（帶糾錯代碼的全速同步二級緩存）。
奔騰III處理器支持100兆赫的前端總線。
Intel Celeron處理器集成了P6 Dynamic Execution微體系結(jié)構(gòu)和Intel貨幣市場交易? 媒體增強技術(shù)。Celeron處理器還有兩個16 KB L1緩存、指令和數(shù)據(jù)，以及一個128 KB的統(tǒng)一非阻塞二級緩存。賽揚處理器支持66兆赫的前端總線。
車載存儲器可用的內(nèi)存記憶體XVME-660有一個用于單個144針SODIMM的插槽，可提供多達256 MB的SDRAM。XVME-660配置包括32 MB、64 MB、128 MB和256 MB。批準的SDRAM供應(yīng)商列于附錄A中。
閃存BIOSXVME-660系統(tǒng)BIOS包含在512 KB閃存設(shè)備中，以方便系統(tǒng)BIOS更新。
啟動ROM站點此32針板載站點在生產(chǎn)過程中用于用引導(dǎo)ROM閃存BIOS。正常操作期間不應(yīng)使用該場地。
The XVME-660 VMEbus Intel? Celeron?/Pentium? III PC-compatible VMEbus processor module combines the high performance and ruggedized packaging of the VMEbus
with the broad application software base of the IBM PC/AT standard. It integrates the
latest processor and chipset technology.
Module Features
The XVME-660 offers the following features:
Intel Celeron 566 MHz or Pentium III 700 MHz Socket 370 based CPU
66 MHz (Celeron processor) or 100 MHz (Pentium III processor) frontside bus
Up to 256 MB SDRAM (one 144-pin SODIMM)
128 KB (Celeron processor) or 256 KB (Pentium III processor) on-chip L2 cache
High-performance, 64-bit AGP graphics controller with 4 MB SDRAM
PCI enhanced IDE controller with DMA-33
PCI SCSI controller, 16-bit UltraSCSI up to 40 MBps
10/100 Mbps PCI Ethernet controller with front RJ-45 connector
IDE compact flash site (uses secondary IDE controller)
PCI-to-VMEbus interface with DMA
Two high-speed 16550-compatible serial ports; COM1 configurable to RS-485 or
RS-232C
Universal Serial Bus (USB) port
EPP/ECP configurable parallel port
PS/2-style keyboard and mouse ports
Industry Pack (IP) expansion site
PCI Mezzanine Card (PMC) expansion site (5 V)
Watchdog timer
Configurable hardware byte-swapping logic
Architecture
CPU Chip
The Intel Pentium III processor integrates P6 Dynamic Execution microarchitecture, Dual
Independent Bus (DIB) Architecture, a multi-transaction system bus, Intel MMX? media enhancement technology, and the Intel Processor Serial Number. In addition, it offers
Internet Streaming SIMD Extensions, 70 new instructions enabling advanced imaging,
3D, streaming audio and video, and speech recognition. The Intel Pentium III processor
also has two16 KB L1 caches, instruction and data, and one 256 KB Advanced Transfer Cache (full speed, synchronous L2 cache with Error Correcting Code). The Pentium III
processor supports a 100 Mhz front-side bus.
The Intel Celeron Processor integrates P6 Dynamic Execution microarchitecture and Intel
MMX? media enhancement technology. The Celeron processor also has two16 KB L1
caches, instruction and data, and one 128 KB unified, non-blocking L2 cache. The Celeron processor supports a 66 Mhz front-side bus.
Onboard Memory
SDRAM Memory
The XVME-660 has a socket for a single 144-pin SODIMM, providing up to 256 MB of
SDRAM. The XVME-660 configurations include 32 MB, 64 MB, 128 MB, and 256 MB.
Approved SDRAM suppliers are listed in Appendix A.
Flash BIOS
The XVME-660 system BIOS is contained in a 512 KB flash device to facilitate system
BIOS updates.
Boot ROM Site
This 32-pin onboard site is used during manufacture to flash the BIOS with a boot ROM.
This site should not be used during normal operation.
