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MTL 8939-HN工業(yè)保護(hù)器
PCI BIOS函數(shù)調(diào)用可用的函數(shù)調(diào)用用于標(biāo)識(shí)資源的位置和訪問(wèn)VMEbus接口的配置空間。特殊功能允許讀取和在配置空間中寫(xiě)入單個(gè)字節(jié)、字和DWORD。PCI BIOS例程（對(duì)于16位和32位調(diào)用者）必須以適當(dāng)?shù)臋?quán)限調(diào)用，以便可以啟用/禁用中斷，例程可以訪問(wèn)I/O空間。XVME-660中集成了軟件可選字節(jié)交換硬件，以允許：對(duì)于Intel和Motorola字節(jié)排序方案之間的差異，允許輕松通過(guò)VMEbus進(jìn)行通信。字節(jié)交換包包含多個(gè)緩沖區(qū)，用于直接傳遞數(shù)據(jù)或在傳遞數(shù)據(jù)字節(jié)時(shí)交換數(shù)據(jù)通過(guò)字節(jié)排序方案摩托羅拉系列處理器存儲(chǔ)數(shù)據(jù)，最低有效字節(jié)位于最高地址和最低地址的最高有效字節(jié)。這是指作為大端總線，是VMEbus標(biāo)準(zhǔn)。英特爾系列處理器存儲(chǔ)數(shù)據(jù)以相反的方式，最低有效字節(jié)位于最低地址，并且位于最高地址的最高有效字節(jié)。這被稱(chēng)為小端（或PCI）總線。這種基本差異如圖4-1所示，其中顯示了兩種體系結(jié)構(gòu)存儲(chǔ)的32位量，從地址mt開(kāi)始XVME-660包含一個(gè)通用芯片，該芯片在PCI總線（英特爾體系結(jié)構(gòu)）和VMEbus（摩托羅拉體系結(jié)構(gòu)）之間執(zhí)行地址不變轉(zhuǎn)換，以及字節(jié)交換硬件，以逆轉(zhuǎn)通用芯片字節(jié)通道交換。
顯示了PCI總線和VMEbus之間的地址不變轉(zhuǎn)換。
請(qǐng)注意，PCI（英特爾）總線的內(nèi)部數(shù)據(jù)存儲(chǔ)方案與此不同VME（摩托羅拉）總線的。例如，存儲(chǔ)字節(jié)78（最低有效字節(jié)）而字節(jié)78存儲(chǔ)在PCI機(jī)器上的位置M+3VMEbus機(jī)器。因此，架構(gòu)之間的數(shù)據(jù)總線連接必須映射的正確數(shù)字一致性或數(shù)據(jù)一致性是指XVME-660和VMEbus，其中上述字節(jié)排序方案為在16位或32位量的傳輸期間保持。數(shù)值一致性是通過(guò)將XVME-660緩沖區(qū)設(shè)置為直接傳遞數(shù)據(jù)來(lái)實(shí)現(xiàn)，這允許用于執(zhí)行地址不變字節(jié)通道交換的Universe芯片。數(shù)值一致性用于傳輸整數(shù)數(shù)據(jù)、浮點(diǎn)數(shù)據(jù)、指針等長(zhǎng)字值12345678h由XVME-660和VMEbus存儲(chǔ)在地址M，如圖4-3所示。由于通用芯片，數(shù)據(jù)必須直接通過(guò)字節(jié)交換傳遞硬件為此，在保持?jǐn)?shù)值一致性的情況下，通過(guò)將閃存分頁(yè)和字節(jié)交換寄存器（寄存器234h）的位6和7設(shè)置為設(shè)置為0（與非字節(jié)交換板相同）；參見(jiàn)第17頁(yè)。也就是說(shuō)，硬件字節(jié)交換被禁用，因此tundra數(shù)據(jù)不變量處于活動(dòng)狀態(tài)。
PCI BIOS Function Calls
The available function calls are used to identify the location of resources and to access
configuration space of the VMEbus interface. Special functions allow the reading and
writing of individual bytes, words, and dwords in the configuration space. PCI BIOS routines (for both 16- and 32-bit callers) must be invoked with appropriate privilege so that
interrupts can be enabled/disabled and the routines can access I/O space. Software selectable byte-swapping hardware is integrated into the XVME-660 to allow
for the difference between the Intel and Motorola byte-ordering schemes, allowing easy
communication over the VMEbus. The byte-swapping package incorporates several buffers either to pass data straight through or to swap the data bytes as they are passed
through. Byte-Ordering Schemes
The Motorola family of processors stores data with the least significant byte located at
the highest address and the most significant byte at the lowest address. This is referred to
as a big-endian bus and is the VMEbus standard. The Intel family of processors stores
data in the opposite way, with the least significant byte located at the lowest address and
the most significant byte located at the highest address. This is referred to as a little-endian (or PCI) bus. This fundamental difference is illustrated in Figure 4-1, which
shows a 32-bit quantity stored by both architectures, starting at address MThe XVME-660 contains a Universe chip that performs address-invariant translation between the PCI bus (Intel architecture) and the VMEbus (Motorola architecture), and
byte-swapping hardware to reverse the Universe chip byte-lane swapping. (Contact Tundra at www.tundra.com for a PDF version of the Universe manual.) Figure 4-2 shows address-invariant translation between a PCI bus and a VMEbus. Notice that the internal data storage scheme for the PCI (Intel) bus is different from that
of the VME (Motorola) bus. For example, the byte 78 (the least significant byte) is stored
at location M on the PCI machine while the byte 78 is stored at the location M+3 on the
VMEbus machine. Therefore, the data bus connections between the architectures must be
mapped correctlyNumeric consistency, or data consistency, refers to communications between the
XVME-660 and the VMEbus in which the byte-ordering scheme described above is
maintained during the transfer of a 16-bit or 32-bit quantity. Numeric consistency is
achieved by setting the XVME-660 buffers to pass data straight through, which allows
the Universe chip to perform address-invariant byte-lane swapping. Numeric consistency
is desirable for transferring integer data, floating-point data, pointers, etc. Consider the
long word value 12345678h stored at address M by both the XVME-660 and the VMEbus, as shown in Figure 4-3. Due to the Universe chip, the data must be passed straight through the byte-swapping
hardware. To do this, maintaining numeric consistency, enable the straight-through buffers by setting bits 6 and 7 of the Flash Paging and Byte Swap register (register 234h) both
to 0 (same as non-byte swap board); see p. 17. That is, hardware byte swapping is disabled, so tundra data invariation is active.
