產(chǎn)品內(nèi)容介紹
5X00502G01數(shù)字量輸入卡件
12-PULSE LOGIC功能塊參數(shù)（S13/16）。如果兩個轉(zhuǎn)換器中的實際電流沒有并聯(lián)下降，并且沒有預(yù)期下降，那么延遲時間在REV_delay時間結(jié)束后開始，以使系統(tǒng)能夠自我糾正。在此期間，反轉(zhuǎn)被阻止。延遲時間以倍數(shù)定義循環(huán)數(shù)（參見REV_DELAY）。橋接器反轉(zhuǎn)將獨立于另一個轉(zhuǎn)換器的實際電流信號（如果時間已過）。功能是獨立于控制模式（6或12脈沖或DCF模式）。此參數(shù)必須具有主控形狀和從動形狀的設(shè)置相同。（S21.232中HL較高）FREV_DELAY12-PULSE LOGIC功能塊參數(shù)（S13/16）。
當電流參考極性反轉(zhuǎn)時，此延遲時間開始。如果電橋反轉(zhuǎn)成功，此延遲時間被重置。如果橋接器反轉(zhuǎn)失敗經(jīng)過該時間后，將顯示故障消息F65。
逆轉(zhuǎn)可能失敗，因為一個轉(zhuǎn)換器交換了橋接器或轉(zhuǎn)換器交叉交換橋接器其他的東西。最后，兩個轉(zhuǎn)換器的電流不會增加橋該延遲時間定義為循環(huán)的倍數(shù)（參見REV_delay）。功能獨立于控制模式（6或12脈沖或DCF模式）。此參數(shù)必須在主控形狀和從動形狀上具有相同的設(shè)置，并且必須大于REV_DELAY和REV_GAP加上安全裕度。（S21.232中HL較高）
12-PULSE LOGIC功能塊的輸入（S13/16）。
指向模擬硬件輸入的指針。默認情況下，模擬輸入2已連接。
在作為12脈沖主控器工作的轉(zhuǎn)換器上，實際電流信號從SLAVE必須連接到硬件并傳輸?shù)酱溯斎搿?br/>
在作為12脈沖SLAVE工作的轉(zhuǎn)換器上，實際電流信號從MASTER必須連接到硬件并傳輸?shù)酱溯斎?。傳遞到此指針的信號在插頭連接器X18:11處輸出通過電纜傳輸?shù)男盘柵c連接的信號相反。這互連可用于故障安全電路。它可以在所有模式下工作。
根據(jù)接線圖，應(yīng)進行以下互連：-如果使用無冗余的12脈沖系統(tǒng)（見INHIB_LOGIC）：
-將此輸入連接到兩個轉(zhuǎn)換器的RDY_ON（10901），主轉(zhuǎn)換器和跟隨者
-如果使用12脈沖冗余系統(tǒng)（見BC-LOGIC）：
-將此輸入連接到兩個轉(zhuǎn)換器的BC_NOT_ZERO（13621），主轉(zhuǎn)換器和追隨者
Parameter of 12-PULSE LOGIC-function block (S13/16 ).
If the actual current doesn′t go down in parallel and as expected in both converters this delay time is started when the time of REV_DELAY has elapsed to enable the system to correct itself. During this time the reversal is blocked. The delay time is defined in multiples of cycles (see REV_DELAY). The bridge reversal will be performed independent of the actual current signal of the other converter, if the time has elapsed. The function is independent of the control mode (6- or 12-pulse or DCF mode). This parameter must have the same setting at the Master and the Follower. (higher HL in S21.232)FREV_DELAY Parameter of 12-PULSE LOGIC-function block (S13/16 ). This delay time is started when the polarity of the current reference is inverted. In case the bridge reversal is successful this delay time is reset. In case the bridge reversal failed the fault message F65 is displayed when the time is elapsed. A reversal may fail because only one converter swapped the bridge or the converters swapped bridges crosswise or something else. At the end the current is not increased at both converters with the same bridge. This delay time is defined in multiples of cycles (see REV_DELAY). ). The function is independent of the control mode (6- or 12-pulse or DCF mode). This parameter must have the same setting at the Master and the Follower and must be greater than the sum of REV_DELAY and REV_GAP plus a safety margin. (higher HL in S21.232)
Input of 12-PULSE LOGIC-function block
(S13/16 ). Pointer to an analog hardware input. In default condition the analog input 2 is connected. At converters working as a 12 pulse MASTER the actual current signal taken out of the SLAVE has to be connected to the hardware and transferred to this input. At converters working as a 12 pulse SLAVE the actual current signal taken out of the MASTER has to be connected to the hardware and transferred to this input.The signal passed to this pointer is outputted at Plug Connector X18:11. The logic level of the signal transferred via the cable is inverted compared the one connected to. This interconnection can be used for a fail-safe circuit. It is operative in all modes. Based on the connection diagram this interconnection should be done: - in case a 12 pulse system without redundancy is in use (see INHIB_LOGIC): - connect this input to RDY_ON (10901) at both converters, the Master and the Follower - in case a 12 pulse system with redundancy is in use (see BC-LOGIC): - connect this input to BC_NOT_ZERO (13621) at both converters, the Master and the Follower
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