IS200VRTDH1D工控模塊控制器
正向電壓
它的額定值為8A平均正向電流和35V反向電壓。3A時(shí)的典型正向電壓為0.4V。二極管僅在斷開(kāi)時(shí)間內(nèi)傳導(dǎo)電流。升壓轉(zhuǎn)換器的峰值反向電壓等于調(diào)節(jié)器輸出電壓。正常運(yùn)行時(shí)的平均正向電流等于輸出電流。頻率補(bǔ)償環(huán)路頻率補(bǔ)償通過(guò)串聯(lián)RC網(wǎng)絡(luò)對(duì)誤差放大器（VC引腳）的輸出進(jìn)行。主極由串聯(lián)電容器和輸出阻抗構(gòu)成(≈50萬(wàn)?) 誤差放大器。極點(diǎn)在2Hz至20Hz的范圍內(nèi)。串聯(lián)電阻器在1kHz至5kHz時(shí)產(chǎn)生“零”，從而提高回路穩(wěn)定性和瞬態(tài)響應(yīng)。第二個(gè)電容器，通常是主補(bǔ)償電容器大小的十分之一，有時(shí)用來(lái)減少VC管腳上的開(kāi)關(guān)頻率波動(dòng)。
VC引腳紋波
是由輸出分壓器衰減的輸出電壓紋波和誤差放大器相乘引起的。如果沒(méi)有第二個(gè)電容器，VC管腳紋波為：VC管腳波紋=VRIPPLE=輸出紋波（VP–P）gm=誤差放大器跨導(dǎo)(≈1500μmho）RC=VC引腳上的串聯(lián)電阻器VOUT=直流輸出電壓1.245（VRIPPLE）（gm）（RC）（VOUT）為防止不規(guī)則切換，VC引腳紋波應(yīng)保持在50mVP–P以下。最壞情況下，VC引腳紋波發(fā)生在最大輸出負(fù)載電流下，如果使用質(zhì)量差（高ESR）的輸出電容器，紋波也會(huì)增加。在VC引腳上添加0.0047μF電容器，可將開(kāi)關(guān)頻率紋波降至幾毫伏。RC的低值也將減少VC引腳紋波，但環(huán)路相位裕度可能不足。
Forward voltage
Its rating is 8A average forward current and 35V reverse voltage. The typical forward voltage at 3A is 0.4V. The diode conducts current only during the off time. The peak reverse voltage of the boost converter is equal to the regulator output voltage. The average forward current during normal operation is equal to the output current. The frequency compensation loop is used to compensate the output of the error amplifier (VC pin) through a series RC network. The main pole consists of a series capacitor and an output impedance (≈ 500000 ?) error amplifier. The poles are in the range of 2Hz to 20Hz. The series resistor produces "zero" at 1kHz to 5kHz, thus improving the loop stability and transient response. The second capacitor, usually one tenth of the size of the main compensation capacitor, is sometimes used to reduce the switching frequency fluctuation on the VC pin.
VC pin ripple
It is caused by multiplication of the output voltage ripple attenuated by output voltage divider and error amplifier. If there is no second capacitor, the ripple of VC pin is: VC pin ripple=VRIPPLE=output ripple (VP – P) gm=transconductance of error amplifier (≈ 1500 μ mho) RC=series resistor VOUT on VC pin=DC output voltage 1.245 (VRIPPLE) (gm) (RC) (VOUT) To prevent irregular switching, the ripple of VC pin should be kept below 50mVP – P. In the worst case, the ripple of VC pin occurs at the maximum output load current. If the output capacitor with poor quality (high ESR) is used, the ripple will also increase. Adding 0.0047 μ F capacitor to VC pin can reduce the switching frequency ripple to several millivolts. The low value of RC will also reduce the ripple of VC pin, but the loop phase margin may be insufficient.
