IS200VAICH1D處理器模塊
計(jì)算滿(mǎn)載電流下的電感器峰值電流
以確保電感器不會(huì)飽和。峰值電流可能明顯高于輸出電流，尤其是在電感更小、負(fù)載更輕的情況下，所以不要忽略這一步驟。粉狀鐵芯是可以原諒的，因?yàn)樗鼈冿柡偷煤茌p，而鐵氧體鐵芯飽和得很快，其他鐵芯材料介于兩者之間。以下公式假設(shè)連續(xù)模式操作，但對(duì)于非連續(xù)模式，其誤差僅略高，因此適用于所有條件。APPLICATIO S I FOR ATIO UU W U 9 LT1370 sn1370 1370fs APPLICATION S I FOR ATIO UUW U測(cè)試了低ESR，因此它們給出了給定卷的最低ESR。為了進(jìn)一步降低ESR，可以并聯(lián)使用多個(gè)輸出電容器。微法的數(shù)值不是特別關(guān)鍵，從22μF到大于500μF的數(shù)值都很好，但你不能在ESR上欺騙大自然。如果你發(fā)現(xiàn)一個(gè)微小的22μF固體鉭電容器，它將具有高ESR，輸出紋波電壓將非常糟糕。
表面安裝電容器
一些典型的固體鉭表面安裝電容器。表1.表面安裝固體鉭電容器ESR和紋波電流E外殼尺寸ESR（最大?) 紋波電流（A）AVX TPS，Sprague 593D 0.1至0.3 0.7至1.1 AVX TAJ 0.7至0.9 0.4 D外殼尺寸AVX TPS，Sprague 593D 0.1至0.3 0.7至1.1 AVX TAJ 0.9至2.0 0.36至0.24 C外殼尺寸AVX TPS 0.2（典型）0.5（典型）AVX TAK 1.8至3.0 0.22至0.17 B外殼尺寸AVX TAJ 2.5至10 0.16至0.08許多工程師聽(tīng)說(shuō)，如果固體鉭電容器承受高浪涌電流，則容易發(fā)生故障。這在歷史上是正確的，AVX型TPS電容器是專(zhuān)門(mén)測(cè)試?yán)擞磕芰Φ模擞繌?qiáng)度不是輸出電容器的關(guān)鍵問(wèn)題。固體鉭電容器在非常高的導(dǎo)通電涌期間發(fā)生故障，這在調(diào)節(jié)器的輸出端不會(huì)發(fā)生。高放電浪涌，例如當(dāng)調(diào)節(jié)器輸出完全短路時(shí)，不會(huì)損壞電容器。單電感升壓穩(wěn)壓器在輸出電容器中具有大的RMS紋波電流，必須對(duì)其進(jìn)行額定以處理電流。計(jì)算公式為：輸出電容器紋波電流（RMS）IRIPPLE（RMS）=IOUT=IOUT VOUT–VIN VIN DC 1–DC DC=開(kāi)關(guān)占空比IPEAK=（IOUT）VIN=最小輸入電壓f=500kHz開(kāi)關(guān)頻率+VOUT VIN VIN（VOUT-VIN）））2（f）（L）（VOUT）
Calculate the inductor peak current at full load current
To ensure that the inductor is not saturated. The peak current may be significantly higher than the output current, especially when the inductance is smaller and the load is lighter, so do not ignore this step. Powdered cores are forgivable because they saturate very lightly, while ferrite cores saturate very quickly, and other core materials fall somewhere in between. The following formula assumes continuous mode operation, but for discontinuous mode, its error is only slightly higher, so it is applicable to all conditions. APPLICATIO S I FOR ATIO UU W U 9 LT1370 sn1370 1370fs APPLICATION S I FOR ATIO UUW U tested low ESR, so they give the lowest ESR for a given volume. To further reduce ESR, multiple output capacitors can be used in parallel. The value of the micro method is not particularly critical. The values from 22 μ F to more than 500 μ F are very good, but you can't cheat nature on ESR. If you find a tiny 22 μ F solid tantalum capacitor, it will have a high ESR and the output ripple voltage will be very bad.
Surface mounted capacitor
Some typical solid tantalum surface mount capacitors. Table 1. Surface mounted solid tantalum capacitors ESR and ripple current E Case size ESR (maximum ?) Ripple current (A) AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1 AVX TAJ 0.7 to 0.9 0.4 D Case size AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1 AVX TAJ 0.9 to 2.0 0.36 to 0.24 C Case size AVX TPS 0.2 (typical) 0.5 (typical) AVX TAK 1.8 to 3.0 0.22 to 0.17 B Case size AVX TAJ 2.5 to 10 0.16 to 0.08 Many engineers have heard that, If solid tantalum capacitors bear high inrush current, they are prone to failure. This is correct in history. AVX TPS capacitor is specially used to test the surge capacity, but the surge strength is not the key problem of the output capacitor. Solid tantalum capacitors fail during very high conduction surges, which do not occur at the output of the regulator. High discharge surge, such as when the regulator output is completely short circuited, will not damage the capacitor. The single inductance boost voltage regulator has a large RMS ripple current in the output capacitor, which must be rated to handle the current. The calculation formula is: output capacitor ripple current (RMS) IRIPPLE (RMS)=IOUT=IOUT VOUT – VIN DC 1 – DC DC=switch duty cycle IPEAK=(IOUT) VIN=minimum input voltage f=500kHz switching frequency+VOUT VIN VIN (VOUT-VIN)) 2 (f) (L) (VOUT)
