EMERSON 1C31129G04控制DCS系統(tǒng)
系統(tǒng)時鐘系統(tǒng)時鐘由振蕩器驅(qū)動。下表定義了各種配置的時鐘頻率。實時時鐘輸入RTC時鐘輸入由控制和定時器PLD生成的1MHz時鐘驅(qū)動。這為MC864xD PIC定時器提供了一個固定的時鐘基準(zhǔn)，軟件可以將其用作已知的定時基準(zhǔn)。4.13.3本地總線控制器時鐘分頻器本地總線控制器（LBC）時鐘輸出連接到PLD，但不由內(nèi)部邏輯使用4.14復(fù)位控制邏輯MVME7100上有多個復(fù)位源。以下源生成板級重置：? 通電? 復(fù)位開關(guān)? 看門狗計時器? 系統(tǒng)控制寄存器（BRD_RST）? VME總線重置板級硬重置為整個SBC生成重置，包括處理器、本地PCI/PCI-X總線、以太網(wǎng)PHY、串行端口、閃存設(shè)備和PLD。如果MVME7100被配置為VME系統(tǒng)控制器，VMEbus和本地Tsi148重置輸入也被重置。4.15實時時鐘電池有一個車載電池支架，可方便地更換+3.0V紐扣電池鋰電池（BR2325），為車載實時時鐘提供備用電源。蓄電池開關(guān)電路提供+3.3V和蓄電池電壓之間的自動切換。
System Clock The system clock is driven by an oscillator. The following table defines the clock frequencies for various configurations.Real Time Clock Input The RTC clock input is driven by a 1MHz clock generated by the Control and Timers PLD. This provides a fixed clock reference for the MC864xD PIC timers which software can use as a known timing reference. 4.13.3 Local Bus Controller Clock Divisor The Local Bus Controller (LBC) clock output is connected to the PLD but is not used by the internal logic 4.14 Reset Control Logic There are multiple sources of reset on the MVME7100. The following sources generate a board level reset: ? Power-up ? Reset switch ? Watchdog timer ? System control register (BRD_RST) ? VMEbus reset A board level hard reset generates a reset for the entire SBC including the processor, local PCI/PCI-X buses, Ethernet PHYs, serial ports, flash devices, and PLD(s). If the MVME7100 is configured as the VME system controller, the VMEbus and local Tsi148 reset input are also reset. 4.15 Real Time Clock Battery There is an on-board battery holder that provides easy replacement of a +3.0V button cell lithium battery (BR2325) which provides back-up power to the on-board Real Time Clock. A battery switching circuit provides automatic switching between the +3.3V and battery voltages.
