PCD231B101 3BHE025541R0101控制模塊,ABB配置手冊(cè)
MASUAT位允許軟件將主機(jī)配置為提供UAT數(shù)據(jù)傳輸能力。設(shè)置MASUAT位到1配置主機(jī)以執(zhí)行未對(duì)齊的VMEbus必要時(shí)循環(huán)。如果位被清除，則MC68030被確認(rèn)，從而中斷未對(duì)齊的轉(zhuǎn)換為多個(gè)對(duì)齊的循環(huán)。這一位是由SYSRESET清除。注意，同時(shí)使主機(jī)提供UAT數(shù)據(jù)傳輸能力，VMEbus規(guī)范要求所有D32從機(jī)都支持它。
PCD231B101 3BHE025541R0101控制模塊位4該位由SYSRESET清除。它應(yīng)該保持暢通。位5設(shè)置MASWP位加速M(fèi)C68030對(duì)VMEbus。但是，應(yīng)謹(jǐn)慎使用。什么時(shí)候MASWP（主寫過賬）設(shè)置，MC68030寫入周期為VMEchip確認(rèn)VMEbus，然后再執(zhí)行實(shí)際上已經(jīng)完成了VMEbus。VMEchip完成寫入自行循環(huán)，允許MC68030繼續(xù)有了新的周期。如果SLVEN位被清除（從禁用），則VMEchip甚至在獲得之前就確認(rèn)VME寫入VMEbus主控權(quán)。如果設(shè)置了SLVEN位，則它會(huì)等到已獲得VMEbus mastership。該位被清除系統(tǒng)重置。注意：如果出現(xiàn)錯(cuò)誤，則不會(huì)通過BERR*通知MC68030在VMEchip完成寫投遞時(shí)發(fā)生周期VMEchip可以編程為中斷MC68030，如果發(fā)生此類事件（WPERREN位在實(shí)用程序中斷掩碼寄存器）。請(qǐng)記住中斷通知可能在事件發(fā)生后很長(zhǎng)時(shí)間內(nèi)發(fā)出錯(cuò)誤。位6 020-應(yīng)始終清除該位。位7 DDTACK-對(duì)于25 MHz電路板，應(yīng)始終清除該位并設(shè)置為32 MHz板。必須更改從配置中的位僅當(dāng)VMEchip控制VMEbus時(shí)。更換從機(jī)的建議步驟配置為：a、 在請(qǐng)求程序配置中設(shè)置DWB位注冊(cè)到1。b、 讀取DHB狀態(tài)位，直到其為1。c、 更改從配置寄存器。d、 將DWB位清除為0。
The MASUAT bit allows software to configure the master to
provide the UAT data transfer capability. Setting the MASUAT
bit to 1 configures the master to execute unaligned VMEbus
cycles when necessary.
If the bit is cleared, the MC68030 is acknowledged so as to break
the unaligned transfer into multiple aligned cycles. This bit is
cleared by SYSRESET.
Note While making it optional for the master to provide the
UAT data transfer capability, the VMEbus
specification requires that all D32 slaves support it.
Bit 4 This bit is cleared by SYSRESET. It should remain cleared.
Bit 5 Setting the MASWP bit speeds up MC68030 writes to the
VMEbus. However, it should be used with caution. When
MASWP (Master Write Posting) is set, MC68030 write cycles to
the VMEbus are acknowledged by the VMEchip, before they
have actually finished on the VMEbus. The VMEchip finishes
the write cycles on its own, allowing the MC68030 to continue
with new cycles. If the SLVEN bit is cleared (slave disabled), the
VMEchip acknowledges VME writes even before it has obtained
VMEbus mastership. If the SLVEN bit is set, then it waits until it
has obtained VMEbus mastership. This bit is cleared by
SYSRESET.
Note The MC68030 is not notified via BERR* if an error
occurs while the VMEchip is finishing a write posted
cycle. The VMEchip can be programmed to interrupt
the MC68030 if such an event occurs (WPERREN bit in
the Utility Interrupt Mask Register). Keep in mind that
interrupt notification could be well after the occurrence
of the error.
Bit 6 020 - This bit should always be cleared.
Bit 7 DDTACK - This bit should always be cleared for 25 MHz boards
and set for 32 MHz boards. The bits in the slave configuration must be changed
only when the VMEchip has control of the VMEbus.
The recommended procedure for changing the slave
configuration is:
a. Set the DWB bit in the requester configuration
register to 1.
b. Read the DHB status bit until it is 1.
c. Change the slave configuration register.
d. Clear the DWB bit to 0.
