SIOC086406-002自動(dòng)化卡件，ABB使用配置說明
EPROM/閃存配置頭（J20）MVME172LX可以訂購(gòu)2MB閃存和兩個(gè)EPROM插槽準(zhǔn)備好安裝EPROM，EPROM位置為標(biāo)準(zhǔn)JEDEC 32引腳DIP支持三種跳線可選密度（256 Kbit x 8；512）的插座Kbit x 8-出廠默認(rèn)值；1 Mbit x 8），此外還允許禁用閃存接下來的四個(gè)表顯示了每個(gè)EPROM插槽的地址范圍四種配置。GPI4（J21引腳9-10）是MC2chip中的控制位ASIC，允許從閃存或EPROM。標(biāo)題J21提供了八個(gè)軟件可讀跳線。這些跳線可以在MC2chip LCSR中作為寄存器讀?。ǖ刂窞?FFF4202D）。
SIOC086406-002自動(dòng)化卡件位0與收割臺(tái)銷1-2相關(guān)；位7與引腳15-16相關(guān)。這個(gè)安裝跳線時(shí)，位值讀取為0，安裝跳線時(shí)，位值讀取為1跳線已拆下。MVME172LX出廠時(shí)附帶如圖所示，J21設(shè)置為除GPI4之外的所有0（所有引腳上的跳線）在下面如果安裝了MVME172BUG固件，則三個(gè)跳線可由用戶定義（即引腳11-12、13-14、15-16）。如果MVME172BUG固件未安裝，七個(gè)跳線可由用戶定義（即針腳1-2、3-4、5-6、，7-8, 11-12, 13-14, 15-16).注：引腳9-10（GPI4）保留用于選擇閃光燈內(nèi)存映射（已安裝跳線）或EPROM內(nèi)存映射（跳線已拆下）。它們不可由用戶定義。地址出現(xiàn)各種EPROM/閃存配置的范圍本章的前一節(jié)中。MVME172LX出廠時(shí)J21設(shè)置為全零（所有引腳上的跳線），GPI4除外。內(nèi)存夾層選項(xiàng)MVME172LX上提供了兩個(gè)100針連接器（J15和J22）容納可選內(nèi)存夾層板。兩個(gè)內(nèi)存MVME172LX提供夾層選項(xiàng)：? 4、8、16MB奇偶校驗(yàn)DRAM? 4、8、16、32、64MB ECC DRAM夾層板可以單獨(dú)使用，也可以組合使用一堆（不超過兩層）。以下連接器選項(xiàng)適用堆疊安排：? 4、8和16MB奇偶校驗(yàn)DRAM板在僅底部；它必須是唯一的閣樓或上層閣樓。
? 所有ECC DRAM板都有兩個(gè)連接器選項(xiàng)：–頂部和底部的連接器–僅底部的連接器；必須是唯一的夾層或上層夾層
EPROM/Flash Configuration Header (J20)
The MVME172LX can be ordered with 2MB of Flash memory and two
EPROM sockets ready for the installation of EPROMs, which may be
ordered separately. The EPROM locations are standard JEDEC 32-pin DIP
sockets that support three jumper-selectable densities (256 Kbit x 8; 512
Kbit x 8 — the factory default; 1 Mbit x 8) and which in addition permit
disabling of the Flash memoryThe next four tables show the address range for each EPROM socket in all
four configurations. GPI4 (J21 pins 9-10) is a control bit in the MC2chip
ASIC that allows reset code to be fetched from Flash memory or from
EPROMs.Header J21 provides eight software-readable jumpers. These jumpers can
be read as a register (at address $FFF4202D) in the MC2chip LCSR. Bit 0
is associated with header pins 1-2; bit 7 is associated with pins 15-16. The
bit values are read as a 0 when the jumper is installed, and as a 1 when the
jumper is removed. The MVME172LX is shipped from the factory with
J21 set to all 0s (jumpers on all pins) except for GPI4, as diagrammed
below.If the MVME172BUG firmware is installed, three jumpers are userdefinable (i.e., pins 11-12, 13-14, 15-16). If the MVME172BUG firmware
is not installed, seven jumpers are user-definable (i.e., pins 1-2, 3-4, 5-6,
7-8, 11-12, 13-14, 15-16).
Note Pins 9-10 (GPI4) are reserved to select either the Flash
memory map (jumper installed) or the EPROM memory map
(jumper removed). They are not user-definable. The address
ranges for the various EPROM/Flash configurations appear
in the preceding section of this chapter.
The MVME172LX is shipped from the factory with J21 set to all zeros
(jumpers on all pins) except for GPI4. Memory Mezzanine Options
Two 100-pin connectors (J15 and J22) are provided on the MVME172LX
to accommodate optional memory mezzanine boards. Two memory
mezzanine options are available for the MVME172LX:
? 4, 8, 16MB parity DRAM
? 4, 8, 16, 32, 64MB ECC DRAM
The mezzanine boards may either be used individually or be combined in
a stack (not more than two deep). The following connector options govern
stacking arrangements:
? The 4, 8, and 16MB parity DRAM board has connectors on the
bottom only; it must be either the only mezzanine or the upper
mezzanine.
? All ECC DRAM boards are available with two connector options:
– Connectors on both the top and bottom
– Connectors on the bottom only; must be either the only
mezzanine or the upper mezzanine
