DEIF TAC-311DG電流變送器,TAC-311DG使用數(shù)據(jù)
內(nèi)存選項(xiàng)以下內(nèi)存選項(xiàng)可用于不同版本的MVME172LX板。DRAM選項(xiàng)MVME172LX提供以下DRAM選項(xiàng)：4MB，8MB或16MB共享DRAM，在夾層上具有可編程奇偶校驗(yàn)?zāi)K上的4MB、8MB、16MB、32MB和64MB ECC DRAM夾層板。非ECC內(nèi)存的DRAM架構(gòu)對(duì)于4MB或8MB是非交叉的，對(duì)于16MB是交叉的。奇偶校驗(yàn)保護(hù)當(dāng)檢測到奇偶校驗(yàn)錯(cuò)誤時(shí)，通過中斷或總線異常啟用。
DEIF TAC-311DG電流變送器DRAM性能在DRAM內(nèi)存部分中指定MVME172 VME中MC2chip編程模型中的控制器嵌入式控制器程序員參考指南。DRAM映射解碼器可以編程以適應(yīng)不同的夾層板的基址和尺寸。機(jī)載DRAM是通過本地總線重置禁用，并且必須在DRAM之前編程可以訪問。請(qǐng)參閱中的MC2chip和MCECC說明MVME172 VME嵌入式控制器程序員參考指南有關(guān)詳細(xì)的編程信息。大多數(shù)DRAM設(shè)備需要一定數(shù)量的訪問周期，然后才能執(zhí)行DRAM完全可以運(yùn)行。通常，該要求由板載刷新電路和正常DRAM初始化。然而軟件應(yīng)確保至少10個(gè)初始化周期對(duì)每個(gè)RAM組執(zhí)行。SRAM選項(xiàng)MVME172LX提供128KB的32位寬板載靜態(tài)RAM在單個(gè)非交錯(cuò)架構(gòu)中，具有板載電池備份。這個(gè)SRAM陣列沒有奇偶校驗(yàn)保護(hù)。車載SRAM和夾層的電池備份功能SRAM由電子營銷EM1275設(shè)備（或等效），支持一次和二次電源。在如果主板電源出現(xiàn)故障，EM1275將檢查電源并切換到電壓較高的電源。如果備用電源的電壓低于兩伏，則EM1275阻止第二個(gè)存儲(chǔ)周期；這允許軟件提供早期警告以避免數(shù)據(jù)丟失。因?yàn)榈诙卧L問可能被阻止在電源故障期間，軟件應(yīng)在依靠數(shù)據(jù)。MVME172LX提供跳線（在J14上），允許任何一種電源將EM1275的電源連接到VMEbus+5V STDBY引腳或至車載電池的一個(gè)電池。例如，主系統(tǒng)備份電源可能是連接到VMEbus+5V STDBY引腳和輔助電源可能是車載電池。如果系統(tǒng)源如果出現(xiàn)故障或板從機(jī)箱中卸下，板載電池接管。
Memory Options
The following memory options are available on the different versions of
MVME172LX boards.
DRAM Options
The MVME172LX offers the following DRAM options: either 4MB,
8MB, or 16MB shared DRAM with programmable parity on a mezzanine
module, or 4MB, 8MB, 16MB, 32MB, and 64MB ECC DRAM on a
mezzanine board. The DRAM architecture for non-ECC memory is noninterleaved for 4MB or 8MB and interleaved for 16MB. Parity protection
is enabled with interrupts or bus exception when a parity error is detected.
DRAM performance is specified in the section on the DRAM Memory
Controller in the MC2chip Programming Model in the MVME172 VME
Embedded Controller Programmer’s Reference Guide.
The DRAM map decoder may be programmed to accommodate different
base address(es) and sizes of mezzanine boards. The onboard DRAM is
disabled by a local bus reset and must be programmed before the DRAM
may be accessed. Refer to the MC2chip and MCECC descriptions in the
MVME172 VME Embedded Controller Programmer’s Reference Guide
for detailed programming information.Most DRAM devices require a certain number of access cycles before the
DRAMs are fully operational. Normally this requirement is met by the
onboard refresh circuitry and normal DRAM initialization. However,
software should insure a minimum of 10 initialization cycles are
performed to each bank of RAM.
SRAM Options
The MVME172LX provides 128KB of 32-bit-wide onboard static RAM
in a single non-interleaved architecture with onboard battery backup. The
SRAM arrays are not parity protected.
The battery backup function for the onboard SRAM and the mezzanine
SRAM is provided by an Electro Marketing EM1275 device (or
equivalent) that supports primary and secondary power sources. In the
event of a main board power failure, the EM1275 checks power sources
and switches to the source with the higher voltage.If the voltage of the backup source is lower than two volts, the EM1275
blocks the second memory cycle; this allows software to provide an early
warning to avoid data loss. Because the second access may be blocked
during a power failure, software should do at least two accesses before
relying on the data.
The MVME172LX provides jumpers (on J14) that allow either power
source of the EM1275 to be connected to the VMEbus +5V STDBY pin or
