BENTLY 330901-05-32-05-02-00電纜存儲(chǔ)電路板時(shí)，如果有電池，則應(yīng)斷開以延長(zhǎng)電池壽命。這在以下方面尤為重要：環(huán)境溫度高。MVME177板，帶備用電池裝運(yùn)時(shí)電池已斷開。電池的電源線暴露在因此，電路板不應(yīng)放置在導(dǎo)電板上表面或儲(chǔ)存在導(dǎo)電袋中，除非拆下電池。注：鋰電池包含易燃材料例如鋰和有機(jī)溶劑。如果電池受到虐待或處理不當(dāng)可能爆裂并點(diǎn)燃，可能導(dǎo)致受傷和/或火災(zāi)。
BENTLY 330901-05-32-05-02-00電纜在處理鋰電池時(shí)，仔細(xì)遵循以下列出的預(yù)防措施，以便防止事故：要從模塊中卸下電池，請(qǐng)小心拉動(dòng)電池從插座。車載DRAMMVME177板載DRAM位于夾層板上。夾層板使用錯(cuò)誤檢查和糾正（ECC）用于糾正單位錯(cuò)誤和檢測(cè)雙位錯(cuò)誤的保護(hù)。當(dāng)出現(xiàn)位錯(cuò)誤時(shí)，可以啟用中斷或總線異常檢測(cè)。內(nèi)存夾層的中斷輸出為連接到VMEchip2 PEIRQ*中斷輸入。可以堆疊兩塊夾層板，以提供256MB的機(jī)載RAM。主板和單個(gè)夾層板一起吃一個(gè)槽。堆疊配置需要兩VME板槽。DRAM是四路交錯(cuò)的，以高效地支持緩存突發(fā)周期。DRAM地圖解碼器可以編程以適應(yīng)不同的基址和夾層板的大小。這個(gè)車載DRAM由本地總線重置禁用，必須在可以訪問DRAM之前編程。請(qǐng)參閱單板計(jì)算機(jī)程序員參考指南中的MCECC有關(guān)詳細(xì)的編程信息。大多數(shù)DRAM設(shè)備在DRAM完全運(yùn)行之前，需要一些訪問周期操作的通常情況下，車載設(shè)備滿足此要求刷新電路和正常DRAM初始化。然而軟件應(yīng)確保至少10個(gè)初始化周期對(duì)每個(gè)RAM組執(zhí)行。
When a board is stored, if the battery is present, it should be
disconnected to prolong battery life. This is especially important at
high ambient temperatures. MVME177 boards with battery backup
are shipped with the batteries disconnected.
The power leads from the battery are exposed on the solder side of
the board, therefore the board should not be placed on a conductive
surface or stored in a conductive bag unless the battery is removed.
Note Lithium batteries incorporate inflammable materials
such as lithium and organic solvents. If lithium
batteries are mistreated or handled incorrectly, they
may burst open and ignite, possibly resulting in injury
and/or fire. When dealing with lithium batteries,
carefully follow the precautions listed below in order to
prevent accidents:To remove the battery from the module, carefully pull the battery
from the socket.
Onboard DRAM
The MVME177 onboard DRAM is located on a mezzanine board.
The mezzanine boards use error checking and correction (ECC)
protection to correct single-bit errors and detect double-bit errors.
Interrupts or bus exception can be enabled when a bit error is
detected. The interrupt output from the memory mezzanine is
connected to the VMEchip2 PEIRQ* interrupt input.Two mezzanine boards may be stacked to provide 256MB of
onboard RAM. The main board and a single mezzanine board
together take one slot. The stacked configuration requires two
VMEboard slots. The DRAM is four-way interleaved to efficiently
support cache burst cycles.
The DRAM map decoder can be programmed to accommodate
different base address(es) and sizes of mezzanine boards. The
onboard DRAM is disabled by a local bus reset and must be
programmed before the DRAM can be accessed. Refer to the
MCECC in the Single Board Computers Programmer's Reference Guide
for detailed programming information. Most DRAM devices
require some number of access cycles before the DRAMs are fully
operational. Normally this requirement is met by the onboard
refresh circuitry and normal DRAM initialization. However,
software should insure a minimum of 10 initialization cycles are
performed to each bank of RAM.
