D674A906U01流量計(jì),ABB中文PDF說(shuō)明書(shū)在線閱讀
VMEchip2中提供了看門(mén)狗定時(shí)器功能。當(dāng)看門(mén)狗定時(shí)器已啟用，必須在編程時(shí)間或超時(shí)?？撮T(mén)狗定時(shí)器可以編程生成：? 系統(tǒng)復(fù)位信號(hào)? 本地重置信號(hào)，或? 超時(shí)時(shí)的板故障信號(hào)參考單板機(jī)程序員手冊(cè)中的VMEchip2有關(guān)詳細(xì)編程信息的參考指南。軟件可編程硬件中斷提供了八個(gè)軟件可編程硬件中斷通過(guò)VMEchip2。這些中斷允許軟件創(chuàng)建硬件中斷。
D674A906U01流量計(jì),參考單板中的VMEchip2計(jì)算機(jī)程序員詳細(xì)編程參考指南信息MVME177為本地總線提供超時(shí)功能。什么時(shí)候計(jì)時(shí)器啟用，本地總線訪問(wèn)超時(shí)，傳輸錯(cuò)誤確認(rèn)（TEA）信號(hào)被發(fā)送到本地總線主機(jī)。這個(gè)超時(shí)值可由軟件選擇：本地總線計(jì)時(shí)器在VMEbus綁定周期內(nèi)不工作。VMEbus綁定周期由VMEbus訪問(wèn)計(jì)時(shí)器計(jì)時(shí)，并且VMEbus全局計(jì)時(shí)器。參考單板中的VMEchip2計(jì)算機(jī)程序員詳細(xì)編程參考指南信息模塊標(biāo)識(shí)軟件區(qū)分MVME177模塊和MVME176模塊使用輸入/輸出控制寄存器（GPI）位3。在…上對(duì)于MVME177，輸入/輸出控制寄存器（GPI）位3為輸出（打開(kāi)）“高”（一）。在MVME176上，輸入/輸出控制寄存器（GPI）位3為“低”（零）硬接線（短路）。定時(shí)性能
本節(jié)提供了MVME177。各種MVME177的設(shè)計(jì)工作頻率為50 MHz或60 MHz（當(dāng)060支持時(shí)）。本地總線到DRAM循環(huán)時(shí)間PCCHIP2和VMEchip2具有相同的本地總線接口與MC68060一樣定時(shí)，因此以下循環(huán)時(shí)間適用于PCCHIP2和VMEchip2。對(duì)板上DRAM的讀取訪問(wèn)需要5個(gè)總線時(shí)鐘周期，總線錯(cuò)誤在當(dāng)前周期中報(bào)告。對(duì)板載DRAM的寫(xiě)入訪問(wèn)需要2個(gè)總線時(shí)鐘周期。突發(fā)讀取訪問(wèn)需要8（5-1-1-1）個(gè)總線時(shí)鐘周期當(dāng)前周期中報(bào)告的錯(cuò)誤。突發(fā)寫(xiě)入周期需要5（2-1-1-1）總線時(shí)鐘周期。
A watchdog timer function is provided in the VMEchip2. When the
watchdog timer is enabled, it must be reset by software within the
programmed time or it times out. The watchdog timer can be
programmed to generate:
? A SYSRESET signal
? Local reset signal, or
? Board fail signal if it times out
Refer to the VMEchip2 in the Single Board Computers Programmer's
Reference Guide for detailed programming information.
Software-Programmable Hardware Interrupts
Eight software-programmable hardware interrupts are provided
by the VMEchip2. These interrupts allow software to create a
hardware interrupt. Refer to the VMEchip2 in the Single Board
Computers Programmer's Reference Guide for detailed programming
information. The MVME177 provides a time-out function for the local bus. When
the timer is enabled and a local bus access times out, a Transfer
Error Acknowledge (TEA) signal is sent to the local bus master. The
time-out value is selectable by software for:The local bus timer does not operate during VMEbus bound cycles.
VMEbus bound cycles are timed by the VMEbus access timer and
the VMEbus global timer. Refer to the VMEchip2 in the Single Board
Computers Programmer's Reference Guide for detailed programming
information. Module Identification
Software distinguishes between an MVME177 module and an
MVME176 module by use of the I/O control register (GPI) bit 3. On
an MVME177, the I/O control register (GPI) bit 3 is out (open) for a
“high” (one). On an MVME176, the I/O control register (GPI) bit 3
is hardwired in (shorted) for a “l(fā)ow” (zero).
Timing Performance
This section provides the performance information for the
MVME177. Various MVME177s are designed to operate at 50 MHz
or 60 MHz (when supported by 060).
Local Bus to DRAM Cycle Times
The PCCchip2 and VMEchip2 have the same local bus interface
timing as the MC68060, therefore the following cycle times also
apply to the PCCchip2 and the VMEchip2. Read accesses toonboard DRAM require 5 bus clock cycles with the bus error
reported in the current cycle. Write accesses to onboard DRAM
require 2 bus clock cycles.
Burst read accesses require 8 (5-1-1-1) bus clock cycles with the bus
error reported in the current cycle. Burst write cycles require 5
(2-1-1-1) bus clock cycles.
