D674A906U01流量計,ABB中文PDF說明書在線閱讀
VMEchip2中提供了看門狗定時器功能。當看門狗定時器已啟用，必須在編程時間或超時。看門狗定時器可以編程生成：? 系統(tǒng)復位信號? 本地重置信號，或? 超時時的板故障信號參考單板機程序員手冊中的VMEchip2有關(guān)詳細編程信息的參考指南。軟件可編程硬件中斷提供了八個軟件可編程硬件中斷通過VMEchip2。這些中斷允許軟件創(chuàng)建硬件中斷。
D674A906U01流量計,參考單板中的VMEchip2計算機程序員詳細編程參考指南信息MVME177為本地總線提供超時功能。什么時候計時器啟用，本地總線訪問超時，傳輸錯誤確認（TEA）信號被發(fā)送到本地總線主機。這個超時值可由軟件選擇：本地總線計時器在VMEbus綁定周期內(nèi)不工作。VMEbus綁定周期由VMEbus訪問計時器計時，并且VMEbus全局計時器。參考單板中的VMEchip2計算機程序員詳細編程參考指南信息模塊標識軟件區(qū)分MVME177模塊和MVME176模塊使用輸入/輸出控制寄存器（GPI）位3。在…上對于MVME177，輸入/輸出控制寄存器（GPI）位3為輸出（打開）“高”（一）。在MVME176上，輸入/輸出控制寄存器（GPI）位3為“低”（零）硬接線（短路）。定時性能
本節(jié)提供了MVME177。各種MVME177的設(shè)計工作頻率為50 MHz或60 MHz（當060支持時）。本地總線到DRAM循環(huán)時間PCCHIP2和VMEchip2具有相同的本地總線接口與MC68060一樣定時，因此以下循環(huán)時間適用于PCCHIP2和VMEchip2。對板上DRAM的讀取訪問需要5個總線時鐘周期，總線錯誤在當前周期中報告。對板載DRAM的寫入訪問需要2個總線時鐘周期。突發(fā)讀取訪問需要8（5-1-1-1）個總線時鐘周期當前周期中報告的錯誤。突發(fā)寫入周期需要5（2-1-1-1）總線時鐘周期。
A watchdog timer function is provided in the VMEchip2. When the
watchdog timer is enabled, it must be reset by software within the
programmed time or it times out. The watchdog timer can be
programmed to generate:
? A SYSRESET signal
? Local reset signal, or
? Board fail signal if it times out
Refer to the VMEchip2 in the Single Board Computers Programmer's
Reference Guide for detailed programming information.
Software-Programmable Hardware Interrupts
Eight software-programmable hardware interrupts are provided
by the VMEchip2. These interrupts allow software to create a
hardware interrupt. Refer to the VMEchip2 in the Single Board
Computers Programmer's Reference Guide for detailed programming
information. The MVME177 provides a time-out function for the local bus. When
the timer is enabled and a local bus access times out, a Transfer
Error Acknowledge (TEA) signal is sent to the local bus master. The
time-out value is selectable by software for:The local bus timer does not operate during VMEbus bound cycles.
VMEbus bound cycles are timed by the VMEbus access timer and
the VMEbus global timer. Refer to the VMEchip2 in the Single Board
Computers Programmer's Reference Guide for detailed programming
information. Module Identification
Software distinguishes between an MVME177 module and an
MVME176 module by use of the I/O control register (GPI) bit 3. On
an MVME177, the I/O control register (GPI) bit 3 is out (open) for a
“high” (one). On an MVME176, the I/O control register (GPI) bit 3
is hardwired in (shorted) for a “l(fā)ow” (zero).
Timing Performance
This section provides the performance information for the
MVME177. Various MVME177s are designed to operate at 50 MHz
or 60 MHz (when supported by 060).
Local Bus to DRAM Cycle Times
The PCCchip2 and VMEchip2 have the same local bus interface
timing as the MC68060, therefore the following cycle times also
apply to the PCCchip2 and the VMEchip2. Read accesses toonboard DRAM require 5 bus clock cycles with the bus error
reported in the current cycle. Write accesses to onboard DRAM
require 2 bus clock cycles.
Burst read accesses require 8 (5-1-1-1) bus clock cycles with the bus
error reported in the current cycle. Burst write cycles require 5
(2-1-1-1) bus clock cycles.
