VMIVME-7807-411001 350-0001007807-411001 B燃機(jī)模塊
該位選擇打印機(jī)選通的自動或手動模式。當(dāng)該位較低時(shí)，打印機(jī)選通由寫入生成打印機(jī)數(shù)據(jù)寄存器（自動模式）。當(dāng)該位較高時(shí)打印機(jī)選通不是通過寫入打印機(jī)數(shù)據(jù)生成的寄存器（手動模式）。該位通過重置清除。位1該位控制自動模式下的打印機(jī)選通定時(shí)。當(dāng)該位較低時(shí)，自動模式下的選通時(shí)間為2微秒。
VMIVME-7807-411001 350-0001007807-411001 B燃機(jī)模塊當(dāng)該位高時(shí)，自動模式中的選通時(shí)間模式為8微秒。選通時(shí)間也是時(shí)間延遲從寫入打印機(jī)數(shù)據(jù)寄存器到打印機(jī)選通。該位通過重置清除。位2該位控制手動模式下的打印機(jī)選通。在手動模式下，軟件必須控制定時(shí)。當(dāng)這個(gè)位低，打印機(jī)選通未激活。當(dāng)此位為高，打印機(jī)選通被激活。該位通過重置清除。位3該位控制輸入主信號。當(dāng)該位較低時(shí)輸入主信號未激活。當(dāng)該位較高時(shí)輸入主信號激活。軟件必須控制打印機(jī)輸入主信號的定時(shí)。該位被清除重置。位設(shè)置和清除指令不應(yīng)用于此控制寄存器。因?yàn)橹袛啾粚?寫入狀態(tài)位，狀態(tài)位為1至指示掛起的中斷，讀-修改-寫序列可能清除掛起的中斷。這些位對DMA控制器的中斷級別進(jìn)行編程生成。級別0不生成中斷。這些位是通過重置清除。位3當(dāng)該位為高位時(shí)，中斷被啟用。中斷是此位低時(shí)禁用。該位通過重置清除。位7當(dāng)該位為高位時(shí)，DMA中斷在以位0-2編程的電平。該位是邊緣敏感的設(shè)置在中斷啟用和DMA完成的前沿（inDMA控制和狀態(tài)寄存器）。當(dāng)1時(shí)，該位被清除或當(dāng)中斷被禁用時(shí)寫入。清除后，它保持清除狀態(tài)，直到中斷啟用的下一個(gè)前沿DMA完成。該位通過重置清除。
This bit selects the auto or manual mode for the printer strobe.
When this bit is low, the printer strobe is generated by a write to
the printer data register (auto mode). When this bit is high, the
printer strobe is not generated by a write to the printer data
register (manual mode). This bit is cleared by reset.
Bit 1 This bit controls the printer strobe timing in the auto mode.
When this bit is low, the strobe time in the auto mode is 2
microseconds. When this bit is high, the strobe time in the auto
mode is 8 microseconds. The strobe time is also the time delay
from the write to the printer data register to the assertion of the
printer strobe. This bit is cleared by reset.
Bit 2 This bit controls the printer strobe in the manual mode. In the
manual mode, the software must control the timing. When this
bit is low, the printer strobe is not activated. When this bit is
high, the printer strobe is activated. This bit is cleared by reset.
Bit 3 This bit controls the Input Prime signal. When this bit is low, the
Input Prime signal is not activated. When this bit is high, the
Input Prime signal is activated. The software must control the
timing of the printer Input Prime signal. This bit is cleared by
reset. Bit set and clear instructions should not be used on this
control register. Because the interrupt is cleared by
writing a 1 to the status bit and the status bit is a 1 to
indicate a pending interrupt, the read-modify-write
sequence may clear a pending interrupt. These bits program the interrupt level the DMA controller
generates. Level 0 does not generate an interrupt. These bits are
cleared by reset.
Bit 3 When this bit is high, the interrupt is enabled. The interrupt is
disabled when this bit is low. This bit is cleared by reset.
Bit 7 When this bit is high, a DMA interrupt is being generated at the
level programmed in bits 0-2. This bit is edge sensitive and it is
set on the leading edge of interrupt enable and DMA DONE (in
DMA Control and Status Register). This bit is cleared when a 1
is written to it or when the interrupt is disabled. When cleared,
it remains cleared until the next leading edge of interrupt enable
and DMA DONE. This bit is cleared by reset.
