TB820-2V2 3BSE013209R1端子模塊，ABB使用方法教程
當(dāng)位被設(shè)置為驅(qū)動(dòng)一條IRQ線時(shí)，它們不得更改。這三個(gè)位可以更改只有當(dāng)它們?nèi)壳宄龝r(shí)，才意味著先前的中斷請(qǐng)求已得到服務(wù)。通過(guò)設(shè)置IACKEN提供的附加功能（請(qǐng)參閱至本文件中的實(shí)用程序中斷掩碼寄存器部分第章）由VMEchip提供，用于向本地處理器在中斷請(qǐng)求（生成）時(shí)已在VMEbus。該寄存器允許MC68030確定VMEchip標(biāo)記的總線錯(cuò)誤條件的原因。
TB820-2V2 3BSE013209R1端子模塊讀取寄存器會(huì)將其所有位清除為0.總線錯(cuò)誤狀態(tài)寄存器僅設(shè)計(jì)為指出最新總線錯(cuò)誤情況的原因（即。，當(dāng)有理由設(shè)置任何位時(shí)，所有其他位已清除）。該寄存器允許軟件設(shè)置VMEbus監(jiān)控器短輸入/輸出中的GCSR寄存器集地圖該寄存器位0-3中包含的值配置GCSR基址的第4-7位。地址線A08-A15固定為0美元。參見(jiàn)表4-9。VMEbus的位1-3地址選擇GCSR中的特定寄存器。這些位因此，除非另有說(shuō)明，否則由SYSRESET設(shè)置為1編程后，GCSR集合不響應(yīng)VMEbus訪問(wèn)。當(dāng)GCSR映射為不響應(yīng)VMEbus訪問(wèn)。對(duì)于示例：位置監(jiān)視器SIGHP和SIGLP。這些位為VMEchip。VMEchip顯示的硬連線ID為%0001。位4位置監(jiān)視器0配置為監(jiān)視雙字節(jié)訪問(wèn)主管短輸入/輸出地址$00F0，單字節(jié)訪問(wèn)短輸入/輸出地址$00F1。清除后，LM0表示對(duì)地址$00F0或$00F1的訪問(wèn)是檢測(cè)。此時(shí)，請(qǐng)求實(shí)用程序中斷級(jí)別2（如果中斷已啟用）。當(dāng)中斷為已確認(rèn)或軟件向其寫(xiě)入1時(shí)。該位設(shè)置為1通過(guò)SYSRESET。見(jiàn)以下注釋。
When the bits are set to drive one of the IRQ lines, they
must not be changed. The three bits may be changed
only when they are all cleared, signifying that the
previous interrupt request has been serviced.
An added function provided by setting IACKEN (refer
to the Utility Interrupt Mask Register section in this
chapter) is provided by the VMEchip to signal the local
processor when the interrupt request (generated
through this register) has been acknowledged on the
VMEbus. This register allows the MC68030 to determine the
cause of a bus error condition flagged by the VMEchip.
Reading the register causes all of its bits to be cleared to
0. The bus error status register is designed to only
indicate the cause of the latest bus error condition (i.e.,
when there is cause to set any of the bits, all other bits
are cleared). This register allows software to set the base address of the
GCSR set of registers in the VMEbus supervisor short I/O
map.
The value contained in bits 0-3 of this register configures
bits 4-7 of the GCSR base address. Address lines A08-A15
are fixed at $0. Refer to Table 4-9. Bits 1-3 of the VMEbus
address select the specific registers in the GCSR. These bits
are set to 1 by SYSRESET, therefore, unless otherwise
programmed, the GCSR set does not respond to VMEbus
accesses. GCSR functions are not enabled when the GCSR
is mapped not to respond to VMEbus accesses. For
example: location monitors SIGHP and SIGLP. These bits provide a unique identification number for the
VMEchip. The VMEchip presents a hardwired ID of %0001.
Bit 4 Location monitor 0 is configured to monitor double-byte
accesses to the supervisor short I/O address $00F0, and singlebyte accesses to the short I/O address $00F1. When cleared,
LM0 indicates that an access to address $00F0 or $00F1 was
detected. At such a time, utility interrupt level 2 is requested (if
the interrupt is enabled). LM0 is set when the interrupt is
acknowledged or when software writes a 1 to it. This bit is set to
1 by SYSRESET. See Note below.
