UAD154A 3BHE026866R0101通訊模塊，ABB培訓(xùn)教程
位置監(jiān)視器1配置為監(jiān)視雙字節(jié)訪問主管短輸入/輸出地址$00F2，單字節(jié)訪問短輸入/輸出地址$00F3。清除后，LM1表示對地址$00F2或$00F3的訪問是檢測。此時(shí)，請求公用事業(yè)中斷級別4（如果中斷已啟用）。當(dāng)中斷為已確認(rèn)或軟件向其寫入1時(shí)。該位設(shè)置為1通過SYSRESET。見以下注釋。位6位置監(jiān)視器2配置為監(jiān)視雙字節(jié)訪問主管短輸入/輸出地址$00F4，單字節(jié)訪問短輸入/輸出地址$00F5。清除后，LM2表示對地址$00F4或$00F5的訪問是檢測。
UAD154A 3BHE026866R0101通訊模塊當(dāng)軟件向其寫入1時(shí)，設(shè)置LM2。此位已設(shè)置通過SYSRESET設(shè)置為1。見以下注釋。位置監(jiān)視器3配置為監(jiān)視雙字節(jié)訪問主管短輸入/輸出地址$00F6，單字節(jié)訪問短輸入/輸出地址$00F7。清除后，LM3表示對地址$00F6或$00F7的訪問是檢測。當(dāng)軟件向其寫入1時(shí)，設(shè)置LM3。此位已設(shè)置通過SYSRESET設(shè)置為1。見以下注釋。GCSR基址配置寄存器必須編程以允許GCSR寄存器組響應(yīng)VMEbus訪問以使此功能啟用。執(zhí)行位置監(jiān)視器的VMEbus主機(jī)循環(huán)必須生成DTACK信號以終止周期SIGLP控制信號允許其他VMEbus主機(jī)中斷MC68030。SIGLP只能從VMEbus。它只能由MC68030清除。當(dāng)VMEbus主機(jī)將SIGLP設(shè)置為1，VMEchip請求一個(gè)級別1個(gè)MC68030中斷（如果此類中斷已啟用）。這個(gè)中斷請求一直保留，直到MC68030向其寫入1。該位由SYSRESET清除。見下文注1。位1 SIGHP控制信號允許其他VMEbus主機(jī)中斷MC68030。SIGHP只能從VMEbus。它只能由MC68030清除。當(dāng)VMEbus主機(jī)將SIGHP設(shè)置為1，VMEchip請求一個(gè)級別5中斷MC68030（如果此類中斷已啟用）。這個(gè)中斷請求一直保留，直到MC68030向其寫入1。該位由SYSRESET清除。見下文注1。位4 BRDFAIL是BRDFAIL*輸入/輸出信號的反射線每當(dāng)信號線被激活時(shí)，狀態(tài)位被設(shè)置為1由VMEchip或看門狗超時(shí)激活
來自PCC。
Location monitor 1 is configured to monitor double-byte
accesses to the supervisor short I/O address $00F2, and singlebyte accesses to the short I/O address $00F3. When cleared,
LM1 indicates that an access to address $00F2 or $00F3 was
detected. At such a time, utility interrupt level 4 is requested (if
the interrupt is enabled). LM1 is set when the interrupt is
acknowledged or when software writes a 1 to it. This bit is set to
1 by SYSRESET. See Note below.
Bit 6 Location monitor 2 is configured to monitor double-byte
accesses to the supervisor short I/O address $00F4, and singlebyte accesses to the short I/O address $00F5. When cleared,
LM2 indicates that an access to address $00F4 or $00F5 was
detected. LM2 is set when software writes a 1 to it. This bit is set
to 1 by SYSRESET. See Note below.Location monitor 3 is configured to monitor double-byte
accesses to the supervisor short I/O address $00F6, and singlebyte accesses to the short I/O address $00F7. When cleared,
LM3 indicates that an access to address $00F6 or $00F7 was
detected. LM3 is set when software writes a 1 to it. This bit is set
to 1 by SYSRESET. See Note below.The GCSR Base Address Configuration Register must
be programmed to allow the GCSR set of registers to
respond to VMEbus accesses for this function to be
enabled.
The VMEbus master that executes the location monitor
cycle must generate the DTACK signal to terminate the
cycle. The SIGLP control signal allows other VMEbus masters to
interrupt the MC68030. SIGLP can only be set from the
VMEbus. It can only be cleared by the MC68030. When a
VMEbus master sets SIGLP to a 1, the VMEchip requests a level
1 interrupt to the MC68030 (if such interrupts are enabled). The
interrupt request remains until the MC68030 writes a 1 to it.
This bit is cleared by SYSRESET. See Note 1 below.
Bit 1 The SIGHP control signal allows other VMEbus masters to
interrupt the MC68030. SIGHP can only be set from the
VMEbus. It can only be cleared by the MC68030. When a
VMEbus master sets SIGHP to a 1, the VMEchip requests a level
5 interrupt to the MC68030 (if such interrupts are enabled). The
interrupt request remains until the MC68030 writes a 1 to it.
This bit is cleared by SYSRESET. See Note 1 below.
Bit 4 BRDFAIL is a reflection of the BRDFAIL* input/output signal
line. The status bit is set to 1 whenever the signal line is
activated by either the VMEchip, or by a watchdog time-out
